knx
ETS configurable knx-stack
rf_physical_layer_cc1101.h
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1 #pragma once
2 
3 #ifndef DeviceFamily_CC13X0
4 
5 #include "config.h"
6 #ifdef USE_RF
7 
8 #include <stdint.h>
9 
10 #include "rf_physical_layer.h"
11 
12 /*----------------------------------[standard]--------------------------------*/
13 #define CC1101_TIMEOUT 2000 // Time to wait for a response from CC1101
14 
15 #define RX_PACKET_TIMEOUT 20 // Wait 20ms for packet reception to complete
16 #define TX_PACKET_TIMEOUT 20 // Wait 20ms for packet reception to complete
17 
18 #ifdef __linux__ // Linux Platform
19  extern void delayMicroseconds (unsigned int howLong);
20 #endif
21 
22 /*----------------------[CC1101 - misc]---------------------------------------*/
23 #define CRYSTAL_FREQUENCY 26000000
24 #define CFG_REGISTER 0x2F // 47 registers
25 #define FIFOBUFFER 0x42 // size of Fifo Buffer +2 for rssi and lqi
26 #define RSSI_OFFSET_868MHZ 0x4E // dec = 74
27 #define TX_RETRIES_MAX 0x05 // tx_retries_max
28 #define ACK_TIMEOUT 250 // ACK timeout in ms
29 #define CC1101_COMPARE_REGISTER 0x00 // register compare 0=no compare 1=compare
30 #define BROADCAST_ADDRESS 0x00 // broadcast address
31 #define CC1101_FREQ_315MHZ 0x01
32 #define CC1101_FREQ_434MHZ 0x02
33 #define CC1101_FREQ_868MHZ 0x03
34 #define CC1101_FREQ_915MHZ 0x04
35 #define CC1101_TEMP_ADC_MV 3.225 // 3.3V/1023 . mV pro digit
36 #define CC1101_TEMP_CELS_CO 2.47 // Temperature coefficient 2.47mV per Grad Celsius
37 
38 /*---------------------------[CC1101 - R/W offsets]---------------------------*/
39 #define WRITE_SINGLE_BYTE 0x00
40 #define WRITE_BURST 0x40
41 #define READ_SINGLE_BYTE 0x80
42 #define READ_BURST 0xC0
43 /*---------------------------[END R/W offsets]--------------------------------*/
44 
45 /*------------------------[CC1101 - FIFO commands]----------------------------*/
46 #define TXFIFO_BURST 0x7F // write burst only
47 #define TXFIFO_SINGLE_BYTE 0x3F // write single only
48 #define RXFIFO_BURST 0xFF // read burst only
49 #define RXFIFO_SINGLE_BYTE 0xBF // read single only
50 #define PATABLE_BURST 0x7E // power control read/write
51 #define PATABLE_SINGLE_BYTE 0xFE // power control read/write
52 /*---------------------------[END FIFO commands]------------------------------*/
53 
54 /*----------------------[CC1101 - config register]----------------------------*/
55 #define IOCFG2 0x00 // GDO2 output pin configuration
56 #define IOCFG1 0x01 // GDO1 output pin configuration
57 #define IOCFG0 0x02 // GDO0 output pin configuration
58 #define FIFOTHR 0x03 // RX FIFO and TX FIFO thresholds
59 #define SYNC1 0x04 // Sync word, high byte
60 #define SYNC0 0x05 // Sync word, low byte
61 #define PKTLEN 0x06 // Packet length
62 #define PKTCTRL1 0x07 // Packet automation control
63 #define PKTCTRL0 0x08 // Packet automation control
64 #define DEVADDR 0x09 // Device address
65 #define CHANNR 0x0A // Channel number
66 #define FSCTRL1 0x0B // Frequency synthesizer control
67 #define FSCTRL0 0x0C // Frequency synthesizer control
68 #define FREQ2 0x0D // Frequency control word, high byte
69 #define FREQ1 0x0E // Frequency control word, middle byte
70 #define FREQ0 0x0F // Frequency control word, low byte
71 #define MDMCFG4 0x10 // Modem configuration
72 #define MDMCFG3 0x11 // Modem configuration
73 #define MDMCFG2 0x12 // Modem configuration
74 #define MDMCFG1 0x13 // Modem configuration
75 #define MDMCFG0 0x14 // Modem configuration
76 #define DEVIATN 0x15 // Modem deviation setting
77 #define MCSM2 0x16 // Main Radio Cntrl State Machine config
78 #define MCSM1 0x17 // Main Radio Cntrl State Machine config
79 #define MCSM0 0x18 // Main Radio Cntrl State Machine config
80 #define FOCCFG 0x19 // Frequency Offset Compensation config
81 #define BSCFG 0x1A // Bit Synchronization configuration
82 #define AGCCTRL2 0x1B // AGC control
83 #define AGCCTRL1 0x1C // AGC control
84 #define AGCCTRL0 0x1D // AGC control
85 #define WOREVT1 0x1E // High byte Event 0 timeout
86 #define WOREVT0 0x1F // Low byte Event 0 timeout
87 #define WORCTRL 0x20 // Wake On Radio control
88 #define FREND1 0x21 // Front end RX configuration
89 #define FREND0 0x22 // Front end TX configuration
90 #define FSCAL3 0x23 // Frequency synthesizer calibration
91 #define FSCAL2 0x24 // Frequency synthesizer calibration
92 #define FSCAL1 0x25 // Frequency synthesizer calibration
93 #define FSCAL0 0x26 // Frequency synthesizer calibration
94 #define RCCTRL1 0x27 // RC oscillator configuration
95 #define RCCTRL0 0x28 // RC oscillator configuration
96 #define FSTEST 0x29 // Frequency synthesizer cal control
97 #define PTEST 0x2A // Production test
98 #define AGCTEST 0x2B // AGC test
99 #define TEST2 0x2C // Various test settings
100 #define TEST1 0x2D // Various test settings
101 #define TEST0 0x2E // Various test settings
102 /*-------------------------[END config register]------------------------------*/
103 
104 /*------------------------[CC1101-command strobes]----------------------------*/
105 #define SRES 0x30 // Reset chip
106 #define SFSTXON 0x31 // Enable/calibrate freq synthesizer
107 #define SXOFF 0x32 // Turn off crystal oscillator.
108 #define SCAL 0x33 // Calibrate freq synthesizer & disable
109 #define SRX 0x34 // Enable RX.
110 #define STX 0x35 // Enable TX.
111 #define SIDLE 0x36 // Exit RX / TX
112 #define SAFC 0x37 // AFC adjustment of freq synthesizer
113 #define SWOR 0x38 // Start automatic RX polling sequence
114 #define SPWD 0x39 // Enter pwr down mode when CSn goes hi
115 #define SFRX 0x3A // Flush the RX FIFO buffer.
116 #define SFTX 0x3B // Flush the TX FIFO buffer.
117 #define SWORRST 0x3C // Reset real time clock.
118 #define SNOP 0x3D // No operation.
119 /*-------------------------[END command strobes]------------------------------*/
120 
121 /*----------------------[CC1101 - status register]----------------------------*/
122 #define PARTNUM 0xF0 // Part number
123 #define VERSION 0xF1 // Current version number
124 #define FREQEST 0xF2 // Frequency offset estimate
125 #define LQI 0xF3 // Demodulator estimate for link quality
126 #define RSSI 0xF4 // Received signal strength indication
127 #define MARCSTATE 0xF5 // Control state machine state
128 #define WORTIME1 0xF6 // High byte of WOR timer
129 #define WORTIME0 0xF7 // Low byte of WOR timer
130 #define PKTSTATUS 0xF8 // Current GDOx status and packet status
131 #define VCO_VC_DAC 0xF9 // Current setting from PLL cal module
132 #define TXBYTES 0xFA // Underflow and # of bytes in TXFIFO
133 #define RXBYTES 0xFB // Overflow and # of bytes in RXFIFO
134 #define RCCTRL1_STATUS 0xFC //Last RC Oscillator Calibration Result
135 #define RCCTRL0_STATUS 0xFD //Last RC Oscillator Calibration Result
136 //--------------------------[END status register]-------------------------------
137 
138 /*----------------------[CC1101 - Main Radio Control State Machine states]-----*/
139 #define MARCSTATE_BITMASK 0x1F
140 #define MARCSTATE_SLEEP 0x00
141 #define MARCSTATE_IDLE 0x01
142 #define MARCSTATE_XOFF 0x02
143 #define MARCSTATE_VCOON_MC 0x03
144 #define MARCSTATE_REGON_MC 0x04
145 #define MARCSTATE_MANCAL 0x05
146 #define MARCSTATE_VCOON 0x06
147 #define MARCSTATE_REGON 0x07
148 #define MARCSTATE_STARTCAL 0x08
149 #define MARCSTATE_BWBOOST 0x09
150 #define MARCSTATE_FS_LOCK 0x0A
151 #define MARCSTATE_IFADCON 0x0B
152 #define MARCSTATE_ENDCAL 0x0C
153 #define MARCSTATE_RX 0x0D
154 #define MARCSTATE_RX_END 0x0E
155 #define MARCSTATE_RX_RST 0x0F
156 #define MARCSTATE_TXRX_SWITCH 0x10
157 #define MARCSTATE_RXFIFO_OVERFLOW 0x11
158 #define MARCSTATE_FSTXON 0x12
159 #define MARCSTATE_TX 0x13
160 #define MARCSTATE_TX_END 0x14
161 #define MARCSTATE_RXTX_SWITCH 0x15
162 #define MARCSTATE_TXFIFO_UNDERFLOW 0x16
163 
164 // Chip Status Byte
165 // Bit fields in the chip status byte
166 #define CHIPSTATUS_CHIP_RDYn_BITMASK 0x80
167 #define CHIPSTATUS_STATE_BITMASK 0x70
168 #define CHIPSTATUS_FIFO_BYTES_AVAILABLE_BITMASK 0x0F
169 // Chip states
170 #define CHIPSTATUS_STATE_IDLE 0x00
171 #define CHIPSTATUS_STATE_RX 0x10
172 #define CHIPSTATUS_STATE_TX 0x20
173 #define CHIPSTATUS_STATE_FSTXON 0x30
174 #define CHIPSTATUS_STATE_CALIBRATE 0x40
175 #define CHIPSTATUS_STATE_SETTLING 0x50
176 #define CHIPSTATUS_STATE_RX_OVERFLOW 0x60
177 #define CHIPSTATUS_STATE_TX_UNDERFLOW 0x70
178 
179 // loop states
180 #define RX_START 0
181 #define RX_ACTIVE 1
182 #define RX_END 2
183 #define TX_START 3
184 #define TX_ACTIVE 4
185 #define TX_END 5
186 
187 class RfDataLinkLayer;
188 
189 class RfPhysicalLayerCC1101 : public RfPhysicalLayer
190 {
191  public:
192  RfPhysicalLayerCC1101(RfDataLinkLayer& rfDataLinkLayer, Platform& platform);
193 
194  bool InitChip();
195  void showRegisterSettings();
196  void stopChip();
197  void loop();
198 
199  private:
200  // Table for encoding 4-bit data into a 8-bit Manchester encoding.
201  static const uint8_t manchEncodeTab[16];
202  // Table for decoding 4-bit Manchester encoded data into 2-bit
203  static const uint8_t manchDecodeTab[16];
204 
205  static const uint8_t cc1101_2FSK_32_7_kb[CFG_REGISTER];
206  static const uint8_t paTablePower868[8];
207 
208  void manchEncode(uint8_t* uncodedData, uint8_t* encodedData);
209  bool manchDecode(uint8_t* encodedData, uint8_t* decodedData);
210 
211  void powerDownCC1101();
212  void setOutputPowerLevel(int8_t dBm);
213 
214  uint8_t sIdle();
215  uint8_t sReceive();
216 
217  void spiWriteRegister(uint8_t spi_instr, uint8_t value);
218  uint8_t spiReadRegister(uint8_t spi_instr);
219  uint8_t spiWriteStrobe(uint8_t spi_instr);
220  void spiReadBurst(uint8_t spi_instr, uint8_t* pArr, uint8_t len);
221  void spiWriteBurst(uint8_t spi_instr, const uint8_t* pArr, uint8_t len);
222 
223  uint8_t _loopState = RX_START;
224 
225  bool syncStart = false;
226  bool packetStart = true;
227  bool fixedLengthMode = false;
228  uint8_t* sendBuffer {0};
229  uint16_t sendBufferLength {0};
230  uint8_t packet[512];
231  uint8_t buffer[sizeof(packet) * 2]; // We need twice the space due to manchester encoding
232  uint8_t* pByteIndex = &buffer[0];
233  uint16_t pktLen {0};
234  uint16_t bytesLeft = {0};
235  uint8_t statusGDO0 {0};
236  uint8_t statusGDO2 {0};
237  uint8_t prevStatusGDO0 {0}; // for edge detection during polling
238  uint8_t prevStatusGDO2 {0}; // for edge detection during polling
239  uint32_t packetStartTime {0};
240 };
241 
242 #endif // USE_RF
243 
244 #endif // DeviceFamily_CC13X0
RfPhysicalLayerCC1101::RfPhysicalLayerCC1101
RfPhysicalLayerCC1101(RfDataLinkLayer &rfDataLinkLayer, Platform &platform)
Definition: rf_physical_layer_cc1101.cpp:135
rf_physical_layer.h
delayMicroseconds
void delayMicroseconds(unsigned int howLong)
Definition: cc1310_platform.cpp:138